#IJSRD
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters
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To design an efficient integrated circuit in terms of Area, Power and speed is one of the challenging task in modern VLSI design field. In the past decade numbers of research have been carried out to optimize design based on area, speed and power utilization. In this paper performance analysis of different available adder architectures has been carried out and then we proposed a Heterogeneous architecture, which composed of four different sub adders to design an adder unit in order to demonstrate trade-offs between performance parameters i.e. Area, Power and speed. In proposed approach the symmetric coefficients of FIR filter area taken into consideration to implement parallel (L=3) FIR filter.
Author(s):
SHANTHA M , ACE, BANGALORE; Ramachandra AC, Dept. of ECE, ACE, Bangalore
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